Programmable logic devices (PLDs) (e.g., field programmable gate arrays (FPGAs), complex programmable logic devices (CPLDs), field programmable systems on a chip (FPSCs), or other types of programmable devices) may be configured with various user designs to implement desired functionality. Typically, the user designs are synthesized and mapped into configurable resources (e.g., programmable logic gates, look-up tables (LUTs), embedded hardware, or other types of resources) and interconnections available in particular PLDs. Physical placement and routing for the synthesized and mapped user designs may then be determined to generate configuration data for the particular PLDs.
Many PLDs today include dedicated memory resources to facilitate efficient implementation of memory components such as random access memories (RAMs), read only memories (ROMs), and first-in first-out (FIFO) memories as may be needed in the user designs. Such dedicated memory resources are typically embedded in PLDs as one or more blocks of static RAM (SRAM), dynamic RAM (DRAM), and/or flash memory that can be configured together with other configurable resources of PLDs to implement memory components having desired functionalities. For example, some embedded memory blocks include circuitry and logic that can be utilized to implement a memory component that can read and write data having mixed widths. That is, those embedded memory blocks support mixed-width mode or mixed-mode memory access and storage where the read data width and the write data width can be different.
However, incorporating the circuitry and logic to support a mixed-width mode may undesirably increase the size and complexity of PLDs having embedded memory blocks, which is especially problematic for low-power, small-footprint PLD, for example, in mobile devices. On the other hand, implementing mixed-width mode memory components of user designs without dedicated circuitry and logic would require user designs to organize multiple embedded memory blocks into particular groupings, which may under-utilize the embedded memory blocks and waste valuable memory resources.
Embodiments of the present disclosure and their advantages are best understood by referring to the detailed description that follows. It should be appreciated that like reference numerals are used to identify like elements illustrated in one or more of the figures.